1. Field of the Invention
The present invention relates to a design for testability method for designing circuits, and more particularly to a design for testability method that forms scan paths in a circuit.
2. Description of the Related Art
Recent years have seen the development of technology for micro-integrating various types of circuit elements such as registers and multiplexers, and LSI (Large Scale Integrated Circuits) and MMIC (Micro Monolithic Integrated Circuits) have been put into practical use as integrated circuit devices.
Such integrated circuit devices comprise a large number of interwired circuit elements such as registers and multiplexers. Scan test is one method of testing such large numbers of circuit elements.
Scan paths, which are signal paths for scan test, are formed in advance in integrated circuit devices in which scan test is carried out. These scan paths enable both input of test signals to the large number of circuit elements and the extraction of output signals from large number of circuit elements.
In designing, register transfer level sequential integrated circuit devices, are converted to gate level sequential integrated circuit devices. At the gate level, FF (flip-flops), which are required elements in an integrated circuit device, are replaced by scan flip-flops for forming scan paths. A large number of scan flip-flops located in an integrated circuit device are connected so as to function as shift registers during execution of a scan test. Scan test signal paths connected in this way are referred to as scan paths. Of these scan paths, the data input terminal of the flip-flop located closest to the fan-in side is connected to the external input terminal, referred to as scan-in, for scan tests. The data output terminal of the flip-flop located closest to the fan-out side is connected to the external output terminal for scan test referred to as fan-out.
All of the flip-flops function as shift registers under the test mode, which is the operation mode of the integrated circuit device during execution of a scan test. Data for testing can therefore be inputted from scan-in and set at flip-flops, and test results held at flip-flops can be outputted from scan-out and observed. The testing problems of sequential circuits can therefore be simplified to the testing problems of combinational circuits.
Design for testability methods of the prior art will next be described with reference to FIGS. 1 to 3.
First, preliminary design is carried out for a register transfer level circuit 1. As shown in FIG. 1, circuit 1 has three 2-bit registers 2-4 and three multiplexers 5-7 as its required circuit elements.
Register 2 is connected to register 3 by way of first multiplexer 5 and second multiplexer 6 in that order. Register 3 is connected to register 4 by way of third multiplexer 7.
In FIG. 1, "R1-R3" indicates that blocks 2-4 are registers, and "M1-M3" indicates that blocks 5-7 are multiplexers. "C1-C5" are processing data, and "Cm1-Cm3" are control signals.
In the first design for testability method of the prior art, in a case in which a preliminary design of circuit 1 has been produced using the required elements as described hereinabove, scan paths are formed by replacing registers 2-4 of circuit 1 by scan flip-flops, as shown in FIGS. 2a and 2b. In FIGS. 2a and 2b as well, "R(1), R(0)" indicates that blocks 2-4 are registers, and "TEST" is a control signal for scan testing.
To describe in greater detail, in a case in which circuit 11 is completed by forming scan paths in preliminarily-designed circuit 1 as shown in FIG. 3, registers 2-4 are replaced by scan flip-flops 12-14, and multiplexer 15 for scan-out is connected to final scan flip-flop 14 as an additional element.
Multiplexer 15 is needed only when existing external output terminals are appropriated as scanout terminals. Therefore, when newly providing scanout terminals, multiplexer 15 can be eliminated.
Scan flip-flops 12-14, are equivalent to a construction in which a multiplexer is inserted as an additional element immediately before the register, which is a required element.
However, the element interiors of scan flip-flops 12-14 are optimized as circuit elements and therefore occupy less area than a case in which multiplexers are simply added immediately before registers 2-4.
"R1, 2, . . . " in FIG. 3 also indicates registers, and "M1, 2, . . . " also indicates multiplexers. "C1, 2, . . . " are processing data and "Cm1, 2, . . . " are control signals. "TEST" is a control signal for scan testing, "SCAN-IN (0), (1)" are test signals to be supplied to circuit 1 in a scan test, and "SCAN-OUT (0), (1)" are test signals to be outputted.
In circuit 11 formed according to the foregoing description, the operating mode of scan flip-flops 12-14 can be switched between normal mode and test mode. Under the test mode, a scan test can be executed by transmitting test signals to scan paths.
In the above-described design for testability method, all registers 2-4 of circuit 1 are simply replaced by scan flip-flops 12-14.
However, "H-SCAN: A High-Level Alternative to Full Scan Testing with Reduced Area and Test Application Overheads" (14.sup.th VLSI Test Symposium 1996, IEEE, pp. 74-80) discloses the appropriation of existing paths inherently in the original design to reduce area overhead associated with forming scan paths.
This design for testability method will be described hereinbelow as the second example of the prior art. Portions equivalent to those of the above-described first example of the prior art are identified using the same reference numerals and redundant explanation is omitted.
Scan paths can be formed by replacing registers 2-4 of circuit 1 by scan flip-flops 12-14 as described hereinabove, but scan flip-flops 12-14 are equivalent to a construction in which multiplexers are inserted immediately before registers 2-4.
In other words, the portions of registers 3 and 4 having multiplexers 5-7 inserted in the preceding sections can form scan paths under the control of multiplexers 5-7.
In the design for testability method of the second example of the prior art, in a case in which multiplexer 22 exists as shown in FIG. 4 as a required element in the section preceding register 21, which is a required element in the preliminary design of a circuit, the path of this portion is extracted as an appropriated path that serves as a scan path, and in accordance with input conditions, a variety of logic gates 23-26 as shown in FIG. 5 are connected as control elements, which are additional elements, to the control terminal of multiplexer 22.
When the path of the preliminary design of circuit 1 is appropriated to form scan paths as described hereinabove, isolated registers not connected to these scan paths may occur.
In a case in which one of registers 27 and 28, which are required elements, is for this reason not connected to the scan paths in the design for testability method according to the second example of the prior art, as shown in FIGS. 6a and 6b, multiplexer 29 is inserted as an additional element between registers 27 and 28 to form a scan path as shown in FIGS. 7a and 7b. The element "C1" shown in the figure is arbitrary circuit element.
If circuit 31 is formed by applying the above-described design for testability method to previously described circuit 1, scan paths can be formed as shown in FIG. 8 by appropriating the path of registers 2-4 or the path of multiplexers 5-7, which are required elements.
In circuit 31 in which scan paths are formed as described hereinabove, multiplexer 32 is inserted as an additional element in the section preceding first register 2, for which a multiplexer does not exist in a preceding section. Control elements composed of inverter 33 and logic gates 34 and 35 are connected as an additional elements to the control terminals of multiplexers 5 and 6, which are required elements located in the section preceding second register 3.
Similarly, a control element made up of inverter 36 and logic gate 37 is connected as an additional element to the control terminal of multiplexer 7, a required element located in the section preceding third register 4. Multiplexer 15 for scan-out is connected as an additional element in the section following third register 4.
In the design for testability method according to the above-described second example of the prior art, the path of required elements 2-7 of the preliminarily-designed circuit 1 is appropriated to form scan paths in order to reduce the area occupied by circuit 31 in which scan paths have been formed.
However, the occupied area of circuit 31 is designed using this design for testability method of the second example of the prior art may be greater than that of circuit 21 designed by the design for testability method of the first example of the prior art.
For example, if the amount of increase in circuit area, i.e., area overhead, for a case in which a register is replaced by scan flip-flop is "2" and the circuit area resulting from the addition of multiplexer 15, which is used as scan-out, is "4," the area overhead for a case in which circuit 11 is designed from circuit 1 based on the design for testability method according to the first example of the prior art for a case in which registers 2-4 of circuit 1 are of 2-bit structure is: EQU (2.times.3).times.2+(4.times.2)=20.
In contrast, if the circuit area of the control elements, which are additional elements, is "1" for each of inverters 33 and 36, "2" for each of AND gates 34 and 37, and "2" for OR gate 35, the area overhead for a case in which circuit 31 is designed from circuit 1 based on the design for testability method according to the second example of the prior art is: EQU (4.times.4)+(2.times.1)+(2.times.2)+(1.times.2)=24.
Although the design for testability method according to the first example of the prior art has smaller area overhead than the second example of the prior art in the above-described examples, the area overhead of the design for testability method according to the second example of the prior art is smaller than the first prior-art example if, for example, the portions of 2-bit structure of the above-described circuit 1 are made 1-bit structure.
Essentially, the design for testability method that realizes the smallest amount of area overhead in circuit area varies according to the configuration of the preliminary-designed circuit, and it is therefore difficult to consistently design a circuit using the optimum design for testability method.
While it is possible to employ such options as designing circuits 11 and 31 using both of the prior-art design for testability methods described hereinabove, comparing the area overhead, and then selecting the optimum method, designing a circuit in this way still does not guarantee that the circuit area overhead will be minimized.